As the telecommunication network continues to evolve from the circuit switching network to the packet switching network, synchronous Ethernet is increasingly being introduced into wireless base station backhaul. Considering the synchronization requirements of the cellular network base station, synchronous Ethernet must be able to achieve synchronous transmission of frequency, support hitless reference clock switching and meet strict standards of holdover performance. Thus, a hitless clock switching system is needed in the clock circuit.
In conventional art, the existing hitless clock switching system preforms tracking synchronization according to a reference clock, and outputs a synchronous clock and phase. Specifically, the tracking refers to dynamically adjusting the local clock by measuring changes in the local clock and reference clock in real time, so that the local clock is always consistent with the reference clock. Synchronization refers to adjusting the clock frequency of the local clock to the same clock frequency as the reference clock.
However, the applicant found that the hitless clock switching system in conventional art has at least the following disadvantages.
When the reference clock (also known as the primary reference clock) is abnormal or missing, the local clock will track and synchronize to a secondary reference clock. If there is a phase deviation between the two reference clocks (the primary reference clock and the secondary reference clock), a phase jitter (for example, TIE) will occur at the instant of switching. Phase jitter is a very important indicator for clock devices, and a clock device with an excessive phase jitter will not pass the standard test, which seriously affects the stability of the communication network.
In addition, the existing hitless clock switching system uses a phase-locked loop (PLL) to synchronize the reference clock phase information. When an abnormality occurs in the primary reference clock, the local clock is synchronized to the secondary reference clock, then clock-compensated by a phase-locked loop to offset the phase difference and outputted. Therefore, at least three phase-locked loops are needed in the existing hitless clock switching system (two phase-locked loops are used for the phase synchronization of the reference clock, and one phase-locked loop is used for the phase adjustment of the output clock), which increases the area of the system, power consumption and complexity.